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Signal Processing
(SP)
Society The Signal Processing Society (SP-1) caters to hardware, firmware and software engineers involved in signal processing techniques, implementation and apparatus.
For upcoming SP lectures and meetings, please visit the
calendar page.
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Organizations > IEEE Global Sig Proc Society Reference |
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Past Lectures |
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Automatic identification of a specific object or pattern in an arbitrary input scene is an important part of any authorization, monitoring and security system. Pattern recognition is always a challenging issue because the targets are often non-cooperative; the scene may contain noise and distortions due to variable environmental conditions during recording the image. Additional requirements for an efficient pattern recognition system are that the architecture should be simple so that it can easily be implemented and be user friendly, and it should perform fast enough to make instantaneous decision on the presence of a target in the input scene. Optical joint transform correlation (JTC) technique has been found to be a versatile tool for real-time pattern recognition applications, which employs optical devices, like lens, spatial light modulator, for parallel processing of the given images. The JTC scheme provides a number of advantages over other correlation techniques, like Vanderlugt filter, in that it allows real-time updating of the reference image, permits parallel Fourier transformation of the reference image and input scene, operates at video frame rates and eliminates the precise positioning requirement of a complex matched filter in the Fourier plane. Several modifications have been proposed to improve the correlation performance of the JTC technique, namely binary JTC, phase-only JTC, fringe-adjusted JTC and shifted phase-encoded fringe-adjusted JTC. This presentation will review the features, problems and prospects of optical pattern recognition techniques.
Programmable electronics on the space station, satellites, and Mars or Venus exploration platforms require extremely small semiconductor chips. Low-power consumption and mixed-signal Field Programmable Gate Arrays (FPGA) devices enable programming with minimal use of batteries, memory chips, and hardwired integrated circuits. FPGA offers improved specifications in the requirements arena of: Low-Power, High-Reliability, Various Environmental Grades, Mixed-Signal Integration, and have a long heritage of success in many Wireless Communications programs. While the pin counts on chips are increasing, the reliability is improving as the speed and throughputs increase. Silicon and Gallium Arsenide semiconductors have increased reliability, in part due to fewer moving or mechanical parts, smaller solder joints, and decreased board or hand-held pad sizes. Chips with single-substrate solutions allow the software program instruction sets to be loaded without an additional fill device or peripheral chips. Remote programming from earth is much easier and is the only method for one way expendables. Highly integrated devices are required and to fit into smaller physical sized products; FPGA product families include Digital, Analog, Clocking, and Memory circuits all on a single device.
High performance image and signal processing applications are significantly benefiting from GP-GPU technology to extract meaningful information from large volumes of rich data sources. This seminar provides an overview of GP-GPU technology and how it can be expected to perform in image and signal processing applications such as target tracking. In addition, we discuss how this technology, which was developed for desktop computing, can be adapted to rugged environmental conditions that are typical of military and aerospace applications.
This seminar features a space-time adaptive processing (STAP) pulsed Doppler Radar simulation using back-end FPGA implementation including: model of a Radar system environment, optimized implementation of STAP back-end processing and FPGA Implementation. Solutions are presented to address challenges often faced by Radar system and implementation engineers. The methodology and tools presented model and simulate systems and algorithms at a high level of abstraction, allow rapid exploration of design options (“what-if” scenarios), while efficiently and optimally implementing designs in FPGAs and ASICs. >
Viewgraphs (0.4 MB) Part I
FPGAs have been used to craft massively parallel custom computing machines since the early 1990s’ and since 2002 they have included embedded multipliers and adders. The next generation of the largest FPGAs from Xilinx, will have an equivalent gate count in the millions and close to 4000 embedded multipliers and adders. The sheer quantity of multipliers and adders allows the designer to build many high throughput DSP functions like digital down-conversion circuits, FFTs, channelizers, etc. However for low throughput requirements it is also possible to use a smaller FPGA device and over-clock (time share) the FPGA resources so as to require less of them. This presentation explores implementation options for efficiently building DSP algorithms like parallel FFTs, channelizers, filters, etc.
The classical theory of variable systems is based on the solutions of linear ordinary differential equations with varying coefficients. The varying coefficients are usually functions of an independent variable, so-called the time variable. The “time variable” is assumed to be a real variable for physical systems. This assumption facilitates analysis and synthesis of fixed (so-called time-invariant) systems by allowing the Laplace transform techniques to be used. However, the assumption of “real time” is shown to be inadequate for realization of time-varying systems in the transformed domain. The discussion in this presentation is based on a different point of view. Specifically, the approach consists essentially in investigating the possibility of system realization through an examination of the behavior of systems that are functions of a complex time-variable. This approach allows, in effect, a two-dimensional Laplace transform technique to be used for the time-varying systems in the same manner that the conventional frequency-domain technique is used in connection with fixed systems. The challenge is the physical interpretation of a “complex time variable” versus the “real time,” and its implications on the transformed variable, so-called the “frequency variable.”
Despite the ever-increasing civilian applications, the main drawback of GPS remains to be its high sensibility to multi-path and interference. The effect of interference on the GPS receiver is to reduce the signal-to-noise ratio (SNR) of the GPS signal such that the receiver is unable to obtain measurements from the GPS satellite. The spread-spectrum (SS) scheme, which underlies the GPS signal structure, provides a certain degree of protection against interference. However, when the interferer power becomes much stronger than the signal power, the spreading gain alone is insufficient to yield any meaningful information. This talk discusses a new technique for anti-jam Global Positioning System (GPS). A novel GPS anti-jam receiver using multi-antenna receivers is introduced which relies on the replications of the coarse/acquisition (C/A) code within a GPS symbol. The proposed receiver utilizes the inherent GPS self-coherence property to excise narrowband and broadband interferers that have different temporal structures from that of the GPS signals.
Third generation wireless communication systems were introduced to extend the data capabilities of second-generation systems by providing quality of service (QoS) management and enabling the high data rates required for high speed web access, and transmission/reception of high quality images and video. To satisfy predicted future increasing demands on even higher rate data services, additional enhancements are being incorporated into the different 3G air interface standards. The first step in evolving the 3G standards is enabling high-speed packet access in the downlink or forward link, i.e. when the terminal is receiving information from the network. The higher data rates are achieved via new features such as adaptive modulation and coding, Hybrid ARQ and fast scheduling. Other enhancements that are being considered are extending the high-speed packet access to the uplink or reverse link (when the terminal is transmitting information to the network) and smart antenna techniques. In this talk we will review the new features recently introduced or being considered for 3G air interfaces and discusses their impact on the performance of the evolving standards.
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2011-12-17 |
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Vice Chairman
Target
Detection Using Optical Joint Transform Correlation
Professor M. Nazrul
Islam - SUNY Farmingdale